The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a guard pattern formed at the border between a cell region and a peripheral region, and a method for forming the same.
A semiconductor memory device includes a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data therein. The transistor is used to transmit data between a bit line and the capacitor in response to a control signal (i.e., a signal on a word line) using the electrical conductivity of the semiconductor memory device that changes depending on environment. The transistor has three regions including a gate, a source and a drain, where charges between the source and the drain move through a channel region in response to the control signal input to the gate.
When a typical transistor is formed using a semiconductor substrate, a gate is formed on the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. In this case, a region between the source and the drain under the gate becomes a channel region of the transistor. The transistor including the horizontal channel region occupies a predetermined area of the semiconductor substrate. Accordingly, it is difficult to reduce the overall area of a complicated semiconductor device since a semiconductor device includes a plurality of transistors.
If the overall area of the semiconductor device is reduced, the number of semiconductor devices capable of being present on each wafer increases, resulting in increased productivity. Accordingly, a variety of methods have been proposed to reduce the overall area of the semiconductor device.
A representative method uses a recess gate instead of a planar gate including a horizontal channel region. With the progress of development of the recessed gate approach, a variety of methods for burying the entirety of the gate in a recess to form a buried gate have recently been proposed.
A conventional method for forming a semiconductor device including a buried gate includes forming a cell region, removing the entirety of materials deposited over a substrate that corresponds to a peripheral region using an open mask for the peripheral region, and forming a transistor in the peripheral region. In such a process, gas injected in an oxidation process for forming a gate oxide film of a transistor in the peripheral region may be applied to a cell transistor in the cell region through a device isolation layer. This may cause a gate oxide film of the cell transistor to be oxidized, resulting in the deterioration of reliability of the gate oxide film of the cell transistor. In order to solve the above-mentioned problem, a guard pattern defined as an active region is formed at the border between the cell region and the peripheral region, such that gas input through the device isolation layer is blocked by the guard pattern.
However, the guard pattern may be damaged in an etch process for opening the cell or peripheral region, resulting in the occurrence of a crack in the guard pattern. The crack may generate a current path between wells, and thus bias leakage failure may occur by the current path.
FIG. 1 illustrates a cross-sectional view of a conventional semiconductor device. FIG. 2 illustrates a cross-sectional view of another conventional semiconductor device. FIG. 3 is a transmission electron microscope (TEM) representation of a cross-sectional view of a conventional semiconductor device including a damaged guard pattern.
Referring to FIG. 1, an active region 14 defined by a device isolation layer 12 is formed in a semiconductor substrate 10 including a cell region (i) and a peripheral region (ii). Subsequently, after a mask pattern 16 defining trenches is formed over the active region 14 and the device isolation layer 12, the active region 14 and the device isolation layer 12 in the cell region (i) are etched using the mask pattern 16 to form trenches.
Subsequently, an electrode material is filled in a lower portion of each trench to form a gate 18 in the trench. An insulation layer 20 and an interlayer insulation film 22 are sequentially formed over the gate 18, and then a conductive layer is buried to form a bit line contact plug 24 over the insulation layer 20.
After that, the interlayer insulation layer 22 formed in the peripheral region (ii) is removed to expose a portion of the device isolation layer 12, which is disposed in a portion of the peripheral region (ii) and adjacent to the cell region (i), and the active region 14 in the peripheral region (ii). As a result, an oxidation path 26 passing through the device isolation layer 12 disposed at the border between the cell region (i) and the peripheral region (ii) is generated in an oxidation process performed during the formation of a transistor in the peripheral region (ii). A gas injected through the oxidation path 26 may be applied to the cell region (i), so that the reliability of the cell gate oxide may be deteriorated.
Turning now to FIG. 2, in order to prevent the oxidation path 26 from being generated, an active region 34 defined by a device isolation layer 32 may be formed in a semiconductor substrate 30 including a cell region (i) and a peripheral region (ii). A guard pattern 36 defined by the device isolation layer 32 is formed at the border 35 between the cell region (i) and the peripheral region (ii).
Subsequently, after a mask pattern 38 defining trenches is formed over the active region 34 and the device isolation layer 32, the active region 34 and the device isolation layer 32 are etched using the mask pattern 38 to form trenches. Subsequently, an electrode material is filled in a lower portion of each trench to form a gate 40 in the trench.
An insulation layer 42 and an interlayer insulation layer 44 are sequentially formed over the gate 40, and then a conductive layer is buried to form a bit line contact plug 46 over the insulation layer 42. After that, the interlayer insulation layer 44 formed in the peripheral region (ii) is removed to expose the device isolation layer 32 and the active region 34 in the peripheral region (ii).
In the case of FIG. 2, an oxidation path 48 passing through the device isolation layer 32 is generated in an oxidation process performed during the formation of a transistor in the peripheral region (ii). However, since the guard pattern 36 is disposed between the cell region (i) and the peripheral region (ii), gas injection to the cell region (i) through the oxidation path 48 is blocked by the guard pattern 36.
As shown in A of FIG. 3, however, the guard pattern 36 may be damaged during a mask/etch process to open the cell region (i) or the peripheral region (ii), so that a crack may be generated in the guard pattern 36. The crack A in the guard pattern 36 may generate a current path between wells and thus cause bias leakage failure.